View CY8C201A0-LDX2I_4811952.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy8c201a0 capsense ? express? slider capacitive controllers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54607 rev. *g revised may 31, 2012 capsense ? express? slider capacitive controllers features capacitive slider and button input ? choice of configurations: ? 10-segment slider ? 5-segment slider with remaining 5 pins configurable as capsense ? or gpio ? robust sensing algorithm ? high sensitivity, low noise ? immunity to rf and ac noise. ? low radiated emc noise ? supports wide range of input capacitance, sensor shapes, and sizes target applications ? printers ? cellular handsets ? lcd monitors ? portable dvd players low operating current ? active current: continu ous sensor scan: 1.5 ma ? deep sleep current: 4 a industry's best configurability ? custom sensor tuning, one optional capacitor ? output supports strong drive for led ? output state can be controlled through i 2 c or directly from capsense input state ? run time reconfigurable over i 2 c advanced features ? interrupt outputs ? user defined inputs ? wake on interrupt input ? sleep control pin ? nonvolatile storage of custom settings ? easy integration into existing products ? configure output to match system ? no external components required ? world class free configuration tool wide range of operating voltages ? 2.4 v to 2.9 v ? 3.10 v to 3.6 v ? 4.75 v to 5.25 v i 2 c communication ? supported from 1.8 v ? internal pull-up resistor support option ? data rate up to 400 kbps ? configurable i 2 c addressing industrial temperature range: ?40 c to +85 c. available in 16-pin qfn and 16-pin soic package overview these capsense express? cont rollers support 4 to 10 capacitive sensing capsense buttons. the device functionality is configured through an i 2 c port and can be stored in onboard nonvolatile memory for automat ic loading at power on. the capsense express controller enables the control of 10 i/os configurable as one capacitive sensing slider (10 segments) [1] or one slider (5 segments) with the rest of the pins as buttons or gpios (for driving leds or interrupt signals based on various button conditions). the four key blocks that make up these devices are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control regi sters with nonvolatile storage, configurable outputs, and i 2 c communications. the user can configure registers with parameters needed to adjust the operation and sensitivity of the capsense buttons and outputs and permanently store the settings. the standard i 2 c serial communication interface enables the host to configure the device and to read sensor information in real time. the i 2 c address is fully configurable without any external hardware strapping. note 1. this part should be selected only if the design requires a slider. this part cannot be confi gured to work without a slider. f or 10 i/o requirements use cy8c20110.
cy8c201a0 document number: 001-54607 rev. *g page 2 of 38 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 pinouts .............................................................................. 4 pin definitions .................................................................. 4 typical circuits ................................................................. 5 i2c interface ...................................................................... 7 i2c device addressing ........ ........................................ 7 i2c clock stretching .................................................... 7 format for register write and read ........................... 8 operating modes of i2c commands ............................... 9 normal mode ............................................................... 9 setup mode ................................................................. 9 device operation modes .................................................. 9 active mode ........... .............. .............. .............. ............ 9 periodic sleep mode ................................................... 9 deep sleep mode ........................................................ 9 sleep control pin .............................................................. 9 interrupt pin to master ..................................................... 9 registers ......................................................................... 10 register map ............................................................. 10 capsense express commands ................................ 14 register conventions ................................................ 14 layout guidelines and best practices ......................... 15 capsense button shapes ......................................... 15 button layout design ................................................ 15 recommended via hole placement .......................... 15 slider shapes ............................................................ 16 dimensions for slider design .................................... 16 example pcb layout design with 5 segment slider, 2 buttons with led backlighting ....................................... 18 operating voltages ......................................................... 19 capsense constraints ................................................... 19 absolute maximum ratings .......................................... 20 operating temperature .................................................. 20 electrical specifications ................................................ 21 dc electrical specifications ...................................... 21 capsense electrical characteristics ......................... 24 ac electrical specifications ....................................... 24 appendix ......................................................................... 27 examples of frequently used i2c commands ......... 27 ordering information ...................................................... 28 ordering code definitions ..... .................................... 28 thermal impedances ...................................................... 28 solder reflow specifications ........................................ 28 package diagrams .......................................................... 29 acronyms ........................................................................ 31 reference documents .................................................... 31 document conventions ................................................. 31 units of measure ....................................................... 31 numeric conventions ............ .................................... 31 glossary .......................................................................... 32 document history page ................................................. 37 sales, solutions, and legal information ...................... 38 worldwide sales and design s upport ......... .............. 38 products .................................................................... 38 psoc solutions ......................................................... 38
cy8c201a0 document number: 001-54607 rev. *g page 3 of 38 important note for information on the preferred dimensions for moun ting qfn packages, see the following application note ?application notes for surface mount assembly of amkor's microleadframe (mlf) packages? available at http://www.amkor.com . pinouts figure 1. 16-pin qfn (3 3 0.6 mm) (no e-pad) pinout ? 5/10 segment slider ? ? 16-pin qfn (no e-pad) ? 5/10 segment slider pin no. name description 1 gp0[0] configurable as capsense or gpio 2 gp0[1] configurable as capsense or gpio 3i 2 c scl i 2 c clock 4i 2 c sda i 2 c data 5 gp1[0] configurable as capsense or gpio 6 gp1[1] [2] configurable as capsense or gpio 7v ss ground connection 8 gp1[2] [2] configurable as capsense or gpio 9 gp1[3] configurable as capsense or gpio 10 gp1[4] configurable as capsense or gpio 11 xres active high external reset with internal pull-down 12 gp0[2] configurable as capsense or gpio 13 v dd supply voltage 14 gp0[3] configurable as capsense or gpio 15 csint integrating capacitor input. the extern al capacitance is required only if 5:1 snr cannot be achieved. typical range is 1 nf to 4.7 nf 16 gp0[4] configurable as capsense or gpio note 2. avoid using gp1[1] and gp1[2] for driving leds. these two pins have special functions during power-up which is used at factor y. leds connected to these two pins blink during device power-up.
cy8c201a0 document number: 001-54607 rev. *g page 4 of 38 pinouts figure 2. 16-pin soic (150 mils) pinout ? 5/10 segment slider ? 16-pin soic ? 5/10 segment slider pin no. name description 1 gp0[3] configurable as capsense or gpio 2 csint integrating capacitor input. the external capacitanc e is required only if 5:1 snr cannot be achieved. typical range is 1 nf to 4.7 nf. 3 gp0[4] configurable as capsense or gpio 4 gp0[0] configurable as capsense or gpio 5 gp0[1] configurable as capsense or gpio 6i 2 c scl i 2 c clock 7i 2 c sda i 2 c data 8 gp1[0] configurable as capsense or gpio 9 gp1[1] [3] configurable as capsense or gpio 10 v ss ground connection 11 gp1[2] [3] configurable as v ss capsense or gpio 12 gp1[3] configurable as capsense or gpio 13 gp1[4] configurable as capsense or gpio 14 xres active high external reset with internal pull-down 15 gp0[2] configurable as capsense or gpio 16 v dd supply voltage note 3. avoid using gp1[1] and gp1[2] for driving leds. these two pins have special functions during power-up which is used at factor y. leds connected to these two pins blink during the device power-up.
cy8c201a0 document number: 001-54607 rev. *g page 5 of 38 typical circuits figure 3. circuit 1 ? five-segment slider with status led and two buttons with backlighting leds figure 4. circuit 2 ? compatibility with 1.8 v i 2 c signaling [4, 5] ? ? notes 4. 1.8 v ? vdd_i2c ? vdd_ce and 2.4 v ? vdd_ce ? 5.25 v. 5. the i2c drive mode of the capsense device should be configured properly before using in an i2c environment with external pull -ups. please refer to i2c_addr_dm register and its factory setting.
cy8c201a0 document number: 001-54607 rev. *g page 6 of 38 figure 5. circuit 3 ? powering down capsense express device for low power requirements [6] typical circuits (continued) master or host ldo capsense express i2c pull ups led i2c bus sda scl vdd output output enable note 6. for low power requirements, if v dd is to be turned off, the concept mentioned in this section can be used. the requirement is that the v dd s of capsense express, i 2 c pull-ups, and leds should be from same source such that turning off the v dd ensures that no signal is applied to the device while it is unpowered. the i 2 c signals should not be driven high by the master in this situation. if a po rt pin or group of port pins of the master can cater to the p ower supply requirements of the circuit, the ldo can be avoided.
cy8c201a0 document number: 001-54607 rev. *g page 7 of 38 i 2 c interface the capsense express devices support the industry standard i 2 c protocol, which can be used for: configuring the device reading the status and dat a registers of the device to control the device operation executing commands the i 2 c address can be modified during configuration. i 2 c device addressing the device uses a seven bit addressing protocol. the i 2 c data transfer is always initiated by the master sending one byte address; the first 7 bit contains address and the last lsb indicates the data transfer direction. zero in the lsb bit indicates the writ e transaction form master and one indicates read transfer by the master . the following table shows the example for different i 2 c addresses. i 2 c clock stretching ?clock stretching? or ?bus stalling? in i 2 c communication protocol is a state in which the slave holds the scl line low to indicate that it is busy. in this condition, the master is expected to wait till the scl is released by the slave. when an i 2 c master communicates with the capsense express device, the capsense express stalls the i 2 c bus after the reception of each byte (that is, just before the ack/nak bit) until processing of the byte is complete and critical internal functions are executed. it is recommended to use a fully i 2 c compliant master to communicate with capsense express device. if an i 2 c master does not support clock stretching (a bit banged software i 2 c master), the master must wait for a specific amount of time (specified in format for register write and read on page 8 ) for each register write and read operation before the next bit is transmitted. check the scl status (should be high) before i 2 c master initiates any data transfer with capsense express. if the master fails to do so and continues to communicate, the communication is incorrect. the following diagrams represent the ack time delays shown in format for register write and read on page 8 for write and read. table 1. i 2 c address examples 7 bit slave address d7 d6 d5 d4 d3 d2 d1 d0 8 bit slave address 1 00000010(w) 02 1 00000011(r) 03 75 10010110(w) 96 75 10010111(w) 97
cy8c201a0 document number: 001-54607 rev. *g page 8 of 38 figure 6. write ack time representation [7] figure 7. read ack time representation [8] format for register write and read register write format register read format legends start slave addr + w a reg addr adata adata a . . . . . data a stop start slave addr + w a reg addr astop start slave addr + r a data a data a . . . . . data nstop master a ? ack slave n ? nak notes 7. time to process the received data. 8. time taken for the device to send next byte.
cy8c201a0 document number: 001-54607 rev. *g page 9 of 38 operating modes of i 2 c commands normal mode in normal mode of operation, the acknowledgment time is optimized. the timings remain approximately the same for different configurations of the slave. to reduce the acknowledgment times in normal mode, the registers 0x06?0x09, 0x0c, 0x0d, 0x10 ?0x17, 0x50, 0x51, 0x57?0x60, 0x7e are given only read access. write to these registers can be done only in setup mode. setup mode all registers have read and write access (except those which are read only) in this mode. the acknowledgment times are longer compared to normal mode. when capsense scanning is disabled (command code 0x0a in command register 0xa0), the acknowledgment times can be improved to values similar to the normal mode of operation. device operation modes capsense express devices are configured to operate in any of the following three modes to meet different power consumption requirements active mode periodic sleep mode deep sleep mode active mode in the active mode, all the devi ce blocks including the capsense sub system are powered. typical active current consumption of the device across the operating voltage range is 1.5 ma. periodic sleep mode sleep mode provides an intermediate power operation mode. it is enabled by configuring the corresponding device registers (0x7e, 0x7f). the device goes into sleep after there is no event for stay awake counter (reg 0x 80) number of sleep intervals. the device wakes up on sleep interval and it scans the capacitive sensors before going back to sleep again. if any sensor is active then the devic e wakes up. the device can also wake up from sleep mode with a gpio interrupt. the following sleep intervals are supported in capsense express. the sleep interval is configured through registers. 1.95 ms (512 hz) 15.6 ms (64 hz) 125 ms (8 hz) 1s (1 hz) deep sleep mode deep sleep mode provides the lowest power consumption because there is no operation running. all capsense scanning is disabled during this mode. in this mode, the device is woken up only using an external gpio interrupt. a sleep timer interrupt cannot wake up a device from deep sleep mode. this is treated as a continuous sleep mode without periodic wakeups. refer to the application note capsense express power and sleep considerations ? an44209 for details on different sleep modes. to get the lowest power durin g this mode the sleep timer frequency should be set to 1 hz. sleep control pin the devices require a dedicated sleep control pin to enable reliable i 2 c communication in case any sleep mode is enabled. this is achieved by pulling the sleep control pin low to wake up the device and start i 2 c communication. the sleep control pin can be configured on any of the gpio. interrupt pin to master to inform the master of any button press, a gpio can be configured as interrupt output and all capsense buttons can be connected to this gpio with or logic operator. this can be configured using the software tool.
cy8c201a0 document number: 001-54607 rev. *g page 10 of 38 registers register map name register address (in hex) access writable only in setup mode [9] factory default values of registers (in hex) i2c max ack time in normal mode (ms) [10] i2c max ack time in setup mode (ms) [10] input_port0 00 r ? 00 0.1 ? input_port1 01 r ? 00 0.1 ? status_por0 02 r ? 00 0.1 ? status_por1 03 r ? 00 0.1 ? output_port0 04 w ? 00 0.1 ? output_port1 05 w ? 00 0.1 ? cs_enabl0 06 rw yes 00 ? 11 cs_enable 07 rw yes 00 ? 11 gpio_enable0 08 rw yes 00 ? 11 gpio_enable1 09 rw yes 00 ? 11 inversion_mask0 0a rw ? 00 0.11 ? inversion_mask1 0b rw ? 00 0.11 ? int_mask0 0c rw yes 00 ? 11 int_mask1 0d rw yes 00 ? 11 status_hold_msk0 0e rw ? 1f 0.11 ? status_hold_msk1 0f rw ? 1f 0.11 ? dm_pull_up0 10 rw yes 00 ? 11 dm_strong0 11 rw yes 00 ? 11 dm_highz0 12 rw yes 00 ? 11 dm_od_low0 13 rw yes 00 ? 11 dm_pull_up1 14 rw yes 00 ? 11 dm_strong1 15 rw yes 00 ? 11 dm_highz1 16 rw yes 00 ? 11 dm_od_low1 17 rw yes 00 ? 11 18 [11] 19 [11] 1a [11] 1b [11] op_sel_00 1c rw ? 00 0.12 11 opr1_prt0_00 1d rw ? 00 0.12 11 opr1_prt1_00 1e rw ? 00 0.12 11 opr2_prt0_00 1f rw ? 00 0.12 11 opr2_prt1_00 20 rw ? 00 0.12 11 op_sel_01 21 rw ? 00 0.12 11 opr1_prt0_01 22 rw ? 00 0.12 11 opr1_prt1_01 23 rw ? 00 0.12 11 notes 9. these registers are writable only after entering into setup mode. all the other registers available for read and write in nor mal and in setup mode. 10. all the ack times specified are max values with all buttons enabled and filer enabled with maximum order. 11. the registers 0x18?0x1b, 0x76, and 0x7d are reserved.
cy8c201a0 document number: 001-54607 rev. *g page 11 of 38 opr2_prt0_01 24 rw ? 00 0.12 11 opr2_prt1_01 25 rw ? 00 0.12 11 op_sel_02 26 rw ? 00 0.12 11 opr1_prt0_02 27 rw ? 00 0.12 11 opr1_prt1_02 28 rw ? 00 0.12 11 opr2_prt0_02 29 rw ? 00 0.12 11 opr2_prt1_02 2a rw ? 00 0.12 11 op_sel_03 2b rw ? 00 0.12 11 opr1_prt0_03 2c rw ? 00 0.12 11 opr1_prt1_03 2d rw ? 00 0.12 11 opr2_prt0_03 2e rw ? 00 0.12 11 opr2_prt1_03 2f rw ? 00 0.12 11 op_sel_04 30 rw ? 00 0.12 11 opr1_prt0_04 31 rw ? 00 0.12 11 opr1_prt1_04 32 rw ? 00 0.12 11 opr2_prt0_04 33 rw ? 00 0.12 11 opr2_prt1_04 34 rw ? 00 0.12 11 op_sel_10 35 rw ? 00 0.12 11 opr1_prt0_10 36 rw ? 00 0.12 11 opr1_prt1_10 37 rw ? 00 0.12 11 opr2_prt0_10 38 rw ? 00 0.12 11 opr2_prt1_10 39 rw ? 00 0.12 11 op_sel_11 3a rw ? 00 0.12 11 opr1_prt0_11 3b rw ? 00 0.12 11 opr1_prt1_11 3c rw ? 00 0.12 11 opr2_prt0_11 3d rw ? 00 0.12 11 opr2_prt1_11 3e rw ? 00 0.12 11 op_sel_12 3f rw ? 00 0.12 11 opr1_prt0_12 40 rw ? 00 0.12 11 opr1_prt1_12 41 rw ? 00 0.12 11 opr2_prt0_12 42 rw ? 00 0.12 11 opr2_prt1_12 43 rw ? 00 0.12 11 op_sel_13 44 rw ? 00 0.12 11 opr1_prt0_13 45 rw ? 00 0.12 11 opr1_prt1_13 46 rw ? 00 0.12 11 opr2_prt0_13 47 rw ? 00 0.12 11 opr2_prt1_13 48 rw ? 00 0.12 11 op_sel_14 49 rw ? 00 0.12 11 opr1_prt0_14 4a rw ? 00 0.12 11 opr1_prt1_14 4b rw ? 00 0.12 11 opr2_prt0_14 4c rw ? 00 0.12 11 register map (continued) name register address (in hex) access writable only in setup mode [9] factory default values of registers (in hex) i2c max ack time in normal mode (ms) [10] i2c max ack time in setup mode (ms) [10]
cy8c201a0 document number: 001-54607 rev. *g page 12 of 38 opr2_prt1_14 4d rw ? 00 0.12 11 cs_noise_th 4e rw ? 28 0.11 11 cs_bl_upd_th 4f rw ? 64 0.11 11 cs_setl_time 50 rw yes a0 ? 35 cs_oth_set 51 rw yes 00 ? 35 cs_hysterisis 52 rw ? 0a 0.11 11 cs_debounce 53 rw ? 03 0.11 11 cs_neg_noise_th 54 rw ? 14 0.11 11 cs_low_bl_rst 55 rw ? 14 0.11 11 cs_filtering 56 rw ? 20 0.11 11 cs_scan_pos_00 57 rw yes ff ? 11 cs_scan_pos_01 58 rw yes ff ? 11 cs_scan_pos_02 59 rw yes ff ? 11 cs_scan_pos_03 5a rw yes ff ? 11 cs_scan_pos_04 5b rw yes ff ? 11 cs_scan_pos_10 5c rw yes ff ? 11 cs_scan_pos_11 5d rw yes ff ? 11 cs_scan_pos_12 5e rw yes ff ? 11 cs_scan_pos_13 5f rw yes ff ? 11 cs_scan_pos_14 60 rw yes ff ? 11 cs_finger_th_00 61 rw ? 64 0.14 11 cs_finger_th_01 62 rw ? 64 0.14 11 cs_finger_th_02 63 rw ? 64 0.14 11 cs_finger_th_03 64 rw ? 64 0.14 11 cs_finger_th_04 65 rw ? 64 0.14 11 cs_finger_th_10 66 rw ? 64 0.14 11 cs_finger_th_11 67 rw ? 64 0.14 11 cs_finger_th_12 68 rw ? 64 0.14 11 cs_finger_th_13 69 rw ? 64 0.14 11 cs_finger_th_14 6a rw ? 64 0.14 11 cs_idac_00 6b rw ? 0a 0.14 11 cs_idac_01 6c rw ? 0a 0.14 11 cs_idac_02 6d rw ? 0a 0.14 11 cs_idac_03 6e rw ? 0a 0.14 11 cs_idac_04 6f rw ? 0a 0.14 11 cs_idac_10 70 rw ? 0a 0.14 11 cs_idac_11 71 rw ? 0a 0.14 11 cs_idac_12 72 rw ? 0a 0.14 11 cs_idac_13 73 rw ? 0a 0.14 11 cs_idac_14 74 rw ? 0a 0.14 11 cs_slid_config 75 rw ? 00 0.1 11 register map (continued) name register address (in hex) access writable only in setup mode [9] factory default values of registers (in hex) i2c max ack time in normal mode (ms) [10] i2c max ack time in setup mode (ms) [10]
cy8c201a0 document number: 001-54607 rev. *g page 13 of 38 76 [12] cs_slid_mulm 77 rw ? 00 0.1 11 cs_slid_mull 78 rw ? 00 0.1 11 i2c_addr_lock 79 rw ? 01 0.11 11 device_id 7a r ? a0 0.11 11 device_status 7b r ? 03 0.11 11 i2c_addr_dm 7c rw ? 00 0.11 11 7d [13] sleep_pin 7e rw yes 00 0.1 11 sleep_ctrl 7f rw ? 00 0.1 11 sleep_sa_cntr 80 rw ? 00 0.1 11 cs_read_button 81 rw ? 00 0.12 11 cs_read_blm 82 r ? 00 0.12 11 cs_read_bll 83 r ? 00 0.12 11 cs_read_diffm 84 r ? 00 0.12 11 cs_read_diffl 85 r ? 00 0.12 11 cs_read_rawm 86 r ? 00 0.12 11 cs_read_rawl 87 r ? 00 0.12 11 cs_read_statusm 88 r ? 00 0.12 11 cs_read_statusl 89 r ? 00 0.12 11 cs_read_cen_posm 8a r ? 00 0.12 11 cs_read_cen_posl 8b r ? 00 0.12 11 cs_read_cen_peakm 8c r ? 00 0.12 11 cs_read_cen_peakl 8d r ? 00 0.12 11 command_reg a0 w ? 00 0.1 11 register map (continued) name register address (in hex) access writable only in setup mode [9] factory default values of registers (in hex) i2c max ack time in normal mode (ms) [10] i2c max ack time in setup mode (ms) [10] notes 12. the registers 0x18?0x1b, 0x76, and 0x7d are reserved. 13. the registers 0x18?0x1b, 0x76, and 0x7d are reserved.
cy8c201a0 document number: 001-54607 rev. *g page 14 of 38 capsense express commands command [14] description executable mode duration the device is not accessible after ack (in ms) w 00 a0 00 get firmware revision setup/normal 0 w 00 a0 01 store current configuration to nvm setup/normal 120 w 00 a0 02 restore factory co nfiguration setup/normal 120 w 00 a0 03 write nvm por defaults setup/normal 120 w 00 a0 04 read nvm por defaults setup/normal 5 w 00 a0 05 read current configurations (ram) setup/normal 5 w 00 a0 06 reconfigure device (por) setup 5 w 00 a0 07 set normal mode of operation setup/normal 0 w 00 a0 08 set setup mode of operation setup/normal 0 w 00 a0 09 start scan setup/normal 10 w 00 a0 0a stop scan setup/normal 5 w 00 a0 0b get capsense scan status setup/normal 0 register conventions this table lists the register conventions that are specific to this section. convention description rw register has both read and write access r register has only read access note 14. the ?w? indicates the write transfer. the next byte of data represents the 7-bit i 2 c address.
cy8c201a0 document number: 001-54607 rev. *g page 15 of 38 layout guidelines and best practices capsense button shapes button layout design x: button to ground clearance (refer to table 2 on page 17 ) y: button to button clearance (refer to table 2 on page 17 ) recommended via hole placement ? ?
cy8c201a0 document number: 001-54607 rev. *g page 16 of 38 slider shapes dimensions for slider design parameter [15] min max recommended width of the segment (a) 2 mm 7 mm equal to overlay thickness clearance between segments (b) 0.5 mm 2 mm equal to sensor to ground clearance height of the segment (c) 7 mm 15 mm 12 mm note 15. the end segments of sliders should be grounded.
cy8c201a0 document number: 001-54607 rev. *g page 17 of 38 table 2. layout guidelines and best practices s. no. category min max recommendations/remarks 1 button shape ? ? solid round pattern, round with led hole, rectangle with round corners 2 button size 5 mm 15 mm 10 mm 3 button-button spacing equal to button ground clearance ? 8 mm [x] 4 button ground clearance 0.5 mm 2 mm button ground clearance = overlay thicknesses 5 slider segment pattern saw tooth pattern 6 number of slider segments 5 10 design can have one 5 segment slider or one 10 segment slider 7 slider segment size 2 mm 5 mm 2 mm 8 slider segment spacing 0.5 mm 2 mm slider segment spacing = overlay thickness 9 ground flood - top layer ? ? hatched ground 7 mil trace and 45 mil grid (15% filling) 10 ground flood - bottom layer ? ? hatched gro und 7 mil trace and 70 mil grid (10% filling) 11 trace length from sensor to psoc buttons ? 200 mm < 100 mm. 12 trace width 0.17 mm 0.20 mm 0.17 mm (7 mil) 13 trace routing ? ? traces should be routed on the non sensor side. if any non capsense trace crosses capsense trace, ensure that intersection is orthogonal. 14 via position for the sensors ? ? via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 15 via hole size for sensor traces ? ? 10 mil 16 number of vias on sensor trace 1 2 1 17 capsense series resistor placement ? 10 mm place capsense series resistors close to the device for noise suppression.capsense resistors have highest priority place them first. 18 distance between any capsense trace to ground flood 10 mil 20 mil 20 mil 19 device placement ? ? mount the device on the layer opposite to sensor. the capsense trace length between the device and sensors should be minimum. 20 placement of components in 2 layer pcb ? ? top layer sensor pads and bottom layer psoc, other components and traces. 21 placement of components in 4 layer pcb ? ? top layer ? sensor pads, second layer ? capsense traces, third layer-hatched ground, bottom layer ? psoc, other components and non capsense traces 22 overlay material ? ? should be non-conductive material (glass, abs plastic, formica) 23 overlay adhesives ? ? adhesive should be non conductive and dielectrically homogenous. 467 mp and 468 mp adhesives made by 3m are recommended. 25 led back lighting ? ? cut a hole in the sensor pad and use rear mountable leds. refer to the pcb layout in the following diagrams. 26 board thickness ? ? standard board thickness for capsense fr4 based designs is 1.6 mm.
cy8c201a0 document number: 001-54607 rev. *g page 18 of 38 the recommended maximum overlay thickness is 5 mm (with external csint)/ 2 mm (without external csint). for more details refer to the section ?the integrating capacitor (cint)? in an53490 . example pcb layout design with 5 segmen t slider, 2 buttons with led backlighting figure 8. top layer figure 9. bottom layer
cy8c201a0 document number: 001-54607 rev. *g page 19 of 38 operating voltages for details on i 2 c 1x ack time, refer to register map on page 10 and register map on page 10 . i2c 4x ack time is approximately four times the values mentioned in these tables. capsense constraints parameter min typ max units notes parasitic capacitance (c p ) of the capsense sensor ? ? 30 pf supply voltage variation (v dd )??+ 5% ?
cy8c201a0 document number: 001-54607 rev. *g page 20 of 38 absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c (0 c to 50 c). extended duration storage temperatures above 65 c degrade reliability t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc voltage on capsense inputs and digital output pins v ss ? 0.5 ? v dd + 0.5 v i mic maximum current into any digs pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch-up current ? ? 200 ma operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c
cy8c201a0 document number: 001-54607 rev. *g page 21 of 38 electrical specifications dc electrical specifications dc chip-level specifications dc gpio specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.10 v to 3.6 v and ?40 c ? t a ? 85 c. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 3. dc chip-level specifications parameter description min typ max unit notes v dd supply voltage 2.40 ? 5.25 v i dd supply current ? 1.5 2.5 ma conditions are v dd = 3.10 v, t a = 25 c i sb deep sleep mode current with por and lvd active ?2.64av dd = 2.55 v, 0 c < t a < 40 c i sb deep sleep mode current with por and lvd active ?2.85av dd = 3.3 v, ?40 c < t a < 85 c i sb deep sleep mode current with por and lvd active ?5.26.4av dd = 5.25 v, ?40 c < t a < 85 c table 4. 5-v and 3.3-v dc gpio specifications parameter description min typ max unit notes v oh1 high output voltage on port 0 pins v dd ? 0.2 ? ? v i oh < 10 a, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v oh2 high output voltage on port 0 pins v dd ? 0.9 ? ? v i oh = 1 ma, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v oh3 high output voltage on port 1 pins v dd ? 0.2 ? ? v i oh < 10 a, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v oh4 high output voltage on port 1 pins v dd ? 0.9 ? ? v i oh = 5 ma, v dd > 3.10 v, maximum of 20 ma source current in all i/os. v ol low output voltage ? ? 0.75 v i ol = 20 ma/pin, v dd > 3.10, maximum of 60 ma sink current on even port pins and of 60 ma sink current on odd port pins. i oh1 high output current on port 0 pins 0.01 ? 1 ma v dd ? 3.1 v, maximum of 20 ma source current in all i/os i oh2 high output current on port 1 pins 0.01 ? 5 ma v dd ? 3.1 v, maximum of 20 ma source current in all i/os i ol low output current ? ? 20 ma v dd ? 3.1 v, maximum of 60 ma sink current on pins p0_2, p1_2, p1_3, p1_4 and 60 ma sink current on pins p0_0, p0_1, p0_3, p0_4, p1_0, p1_1 v il input low voltage ? ? 0.75 v v dd = 3.10 v to 3.6 v. v ih input high voltage 1.6 ? ? v v dd = 3.10 v to 3.6 v. v il input low voltage ? ? 0.8 v v dd = 4.75 v to 5.25 v. v ih input high voltage 2.0 ? ? v v dd = 4.75 v to 5.25 v. v h input hysteresis voltage ? 140 ? mv i il input leakage ? 1 ? na gross tested to 1 a.
cy8c201a0 document number: 001-54607 rev. *g page 22 of 38 this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 2.7 v at 25 c and are for design guidance only. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. temp = 25 c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25 c. table 4. 5-v and 3.3-v dc gpio specifications (continued) parameter description min typ max unit notes table 5. 2.7-v dc gpio specifications parameter description min typ max unit notes v oh1 high output voltage on port 0 pins v dd ? 0.2 ? ? v i oh <10 a, maximum of 10 ma source current in all i/os. v oh2 high output voltage on port 0 pins v dd ? 0.5 ? ? v i oh = 0.2 ma, maximum of 10 ma source current in all i/os. v oh3 high output voltage on port 1 pins v dd ? 0.2 ? ? v i oh < 10 a, maximum of 10 ma source current in all i/os. v oh4 high output voltage on port 1 pins v dd ? 0.5 ? ? v i oh = 2 ma, maximum of 10 ma source current in all i/os. v ol low output voltage ? ? 0.75 v i ol = 10 ma/pin, v dd > 3.10, maximum of 30 ma sink current on even port pins and of 30 ma sink current on odd port pins. [16] i oh high output current 0.01 ? 2 ma v dd ? 2.9 v, maximum of 10 ma source current in all i/os i ol1 low output current on port 0 pins ? ? 10 ma v dd ? 2.9 v, maximum of 30 ma sink current on pins p0_2, p1_2, p1_3, p1_4 and 30 ma sink current on pins p0_0, p0_1, p0_3, p0_4, p1_0, p1_1 i ol2 low output current ? ? 20 ma v dd ? 2.9 v, maximum of 50 ma sink current on pins p0_2, p1_2, p1_3, p1_4 and 50 ma sink current on pins p0_0, p0_1, p0_3, p0_4, p1_0, p1_1 v il input low voltage ? ? 0.75 v v dd = 2.4 to 2.90 v and 3.10 v to 3.6 v. v ih1 input high voltage 1.4 ? ? v v dd = 2.4 to 2.7 v. v ih2 input high voltage 1.6 ? ? v v dd = 2.7 to 2.90 v and 3.10 v to 3.6 v. v h input hysteresis voltage ? 60 ? mv i il input leakage ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. temp = 25 c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25 c. note 16. the maximum sink current is 20 ma for 20140 and 20142 devices and for all other devices the maximum sink current is 30 ma.
cy8c201a0 document number: 001-54607 rev. *g page 23 of 38 dc por specifications dc flash write specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c or 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are fo r design guidance only. flash endurance and retention specificat ions are valid only within the range: 25 c 20 c during the flash writ e operation. it is at the user?s own risk to operate out of this temperature range. if flash writing is done out of this temperature range, th e endurance and data retention reduces. dc i 2 c specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c or 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 6. dc por specifications parameter description min typ max unit notes v ppor0 v ppor1 v dd value for ppor trip v dd = 2.7 v v dd = 3.3 v, 5 v ? ? 2.36 2.60 2.40 2.65 v v v dd must be greater than or equal to 2.5 v during startup or internal reset. vlvd0 vlvd2 vlvd6 v dd value for lvd trip v dd = 2.7 v v dd = 3.3 v v dd = 5 v 2.39 2.75 3.98 2.45 2.92 4.05 2.51 2.99 4.12 v v v table 7. dc flash write specifications symbol description min typ max units notes v ddiwrite supply voltage for flash write operations 2.7 ? ? v i ddp supply current for flash write operations ? 5 25 ma flash enpb flash endurance 50,000 [17] ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years table 8. dc i 2 c specifications symbol [18] description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v ?? v dd ? 2.9 v 3.1 v ?? v dd ? 3.6 v ? ? 0.25 v dd v 4.75 v ? v dd ? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v ? v dd ? 5.25 v v olp low output voltage ? ? 0.4 v i ol = 5 ma/pin c i2c capacitive load on i 2 c pins 0.5 1.7 5 pf package and pin dependent. temp = 25 c ? ? ? ? r pu pull-up resistor 4 5.6 8 ko notes 17. commands involving flash writes (0x01, 0x 02, 0x03) and flash read (0x04) must be executed only within the same vcc voltage r ange detected at por (power on, or command 0x06) and above 2.7 v 18. all gpio meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs .
cy8c201a0 document number: 001-54607 rev. *g page 24 of 38 ac electrical specifications ac chip-level specifications capsense electrical characteristics max (v) typ (v) min (v) conditions for supply voltage result 3.6 3.3 3.1 < 2.9 the device automatically reco nfigures itself to work in 2.7 v mode of operation. > 2.9 or < 3.10 this range is not recommended for capsense usage. 2.90 2.7 2.45 < 2.45 v the scanning for capsen se parameters shuts down until the voltage returns to over 2.45 v. > 3.10 the device automatically reconfigures itself to work in 3.3 v mode of operation. < 2.4 v the device goes into reset. 5.25 5.0 4.75 < 4.73 v the scanning for capsen se parameters shuts down until the voltage returns to over 4.73 v. table 9. 5-v and 3.3-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 15 32 64 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? s t powerup time from end of por to cpu executing code ? 150 ? ms sr power_up power supply slew rate ? ? 250 v/ms table 10. 2.7-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 8 32 96 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? s t powerup time from end of por to cpu executing code ? 600 ? ms sr power_up power supply slew rate ? ? 250 v/ms
cy8c201a0 document number: 001-54607 rev. *g page 25 of 38 ac gpio specifications ac i 2 c specifications table 11. 5-v and 3.3-v ac gpio specifications parameter description min max unit notes t rise0 rise time, strong mode, cload = 50 pf, port 0 15 80 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% t rise1 rise time, strong mode, cload = 50 pf, port 1 10 50 ns v dd = 3.10 v to 3.6 v, 10% ? 90% t fall fall time, strong mode, cload = 50 pf, all ports 10 50 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% table 12. 2.7-v ac gpio specifications parameter description min max unit notes t rise0 rise time, strong mode, cload = 50 pf, port 0 15 100 ns v dd = 2.4 v to 2.90 v, 10% ? 90% t rise1 rise time, strong mode, cload = 50 pf, port 1 10 70 ns v dd = 2.4 v to 2.90 v, 10% ? 90% t fall fall time, strong mode, cload = 50 pf 10 70 ns v dd = 2.4 v to 2.90 v, 10% ? 90% table 13. ac i 2 c specifications parameter description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 kbps fast mode not supported for v dd < 3.0 v t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0?0.6?s t lowi2c low period of the scl clock 4.7 ? 1.3 ? s t highi2c high period of the scl clock 4.0 ? 0.6 ? s t sustai2c setup time for a repeated start condition 4.7?0.6?s t hddati2c data hold time 0 ? 0 ? s t sudati2c data setup time 250 ? 100 ? ns t sustoi2c setup time for stop condition 4.0 ? 0.6 ? s t bufi2c bus free time between a stop and start condition 4.7?1.3?s t spi2c pulse width of spikes suppressed by the input filter ??050ns
cy8c201a0 document number: 001-54607 rev. *g page 26 of 38 figure 10. definition of timing for fast/standard mode on the i 2 c bus i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c201a0 document number: 001-54607 rev. *g page 27 of 38 appendix examples of frequently used i 2 c commands s. no. requirement i 2 c commands [19] comment 1 enter into setup mode w 00 a0 08 2 enter into normal mode w 00 a0 07 3 load factory defaults to ram registers w 00 a0 02 4 do a software reset w 00 a0 08 w 00 a0 06 enter into setup mode do software reset 5 save current configuration to flash w 00 a0 01 6 load factory defaults to ram registers and save as user configuration w 00 a0 08 w 00 a0 02 w 00 a0 01 w 00 a0 06 enter into setup mode load factory defaults to sram save the configuration to flash. wait for time specified in capsense express commands on page 14 . do software reset 7 enable gp00/01/02/03/04/05 and gp10 as capsense button w 00 a0 08 w 00 06 1f 01 w 00 a0 01 w 00 a0 06 enter into setup mode configuring capsense buttons save the configuration to flash. wait for time specified in capsense express commands on page 14 . do software reset 8 enable 5 segment slider w 00 75 01 enable 5 segment slider 8 read capsense button (gp10) scan results w 00 81 81 w 00 82 r 00 rd rd rd rd rd rd select capsense button for reading scan result set the read point to 82h consecutive 6 reads get baseline, difference count and raw count (all two byte each) 9 read capsense button status register w 00 89 r 00 rd set the read pointer to 89 reading a byte gets status capsense inputs 10 read slider centroid position w 00 8a r 00 rd rd set the read pointer to 8a reading a byte gets slider centroid position note 19. the ?w? indicates the write transfer and the next byte of da ta represents the 7-bit i2c address. the i2c address is assumed to be ?0? in the above examples. similarly ?r? indicates the read transfer followed by 7-bit address and data byte read operations.
cy8c201a0 document number: 001-54607 rev. *g page 28 of 38 ordering information ordering code definitions thermal impedances solder reflow specifications ordering code package diagram package type operating temperature capsense block gpios xres pin CY8C201A0-LDX2I 001-09116 16-pin qfn [20] industrial yes 10 yes cy8c201a0-sx2i 51-85068 16-pin soic industrial yes 10 yes table 14. thermal impedances by package package typical ? ja [21] 16-pin qfn[1] 46 c/w 16-pin soic 79.96 c/w temperature range: i = industrial 2 = 16-pin device pb-free package type: xx = ld or s ld = 16-pin qfn; s = 16-pin soic part number family code technology code: c = cmos marketing code: 8 = controllers company id: cy = cypress i c 201 a0 - xx x cy 8 2 table 15. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 16-pin qfn[1] 260 ? c 30 seconds 16-pin soic 260 ? c 30 seconds notes 20. earlier termed as qfn package. 21. t j = t a + power x ? ja.
cy8c201a0 document number: 001-54607 rev. *g page 29 of 38 package diagrams figure 11. 16-pin chip on lead (3 3 0.6 mm) lg16a/ld16a (sawn) package outline, 001-09116 001-09116 *f
cy8c201a0 document number: 001-54607 rev. *g page 30 of 38 figure 12. 16-pin soic (150 mils) s16.15/sz16.15 package outline, 51-85068 package diagrams (continued) 51-85068 *d
cy8c201a0 document number: 001-54607 rev. *g page 31 of 38 acronyms ta b l e 1 6 lists the acronyms that are used in this document. reference documents capsense express power and sleep considerations ? an44209 (001-44209) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . document conventions units of measure ta b l e 1 7 lists the unit sof measures. numeric conventions hexadecimal numbers are represented with all letters in uppercas e with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pr efix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 16. acronyms used in this datasheet acronym description acronym description ac alternating current lsb least-significant bit cmos complementary metal oxide semiconductor lvd low voltage detect dc direct current pcb printed circuit board eeprom electrically erasable programmable read-only memory por power on reset emc electromagnetic compatibility ppor precision power on reset gpio general-purpose i/o psoc ? programmable system-on-chip i/o input/output qfn quad flat no leads idac current dac rf radio frequency ilo internal low speed oscillator so ic small-outline integrated circuit lcd liquid crystal display sram static random access memory ldo low dropout regulator xres external reset led light-emitting diode table 17. units of measure symbol unit of measure symbol unit of measure ? c degree celsius mm millimeter hz hertz ms millisecond kbps kilo bits per second mv millivolt khz kilohertz na nanoampere k ? kilohm ns nanosecond lsb least significant bit % percent a microampere pf picofarad f microfarad v volts s microsecond w watt ma milliampere
cy8c201a0 document number: 001-54607 rev. *g page 32 of 38 glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs , multi-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interf ace between a computer application and lower level services and functions (for example, user m odules and libraries). apis serve as building blo cks for programmers that create software applications. asynchronous a signal whose data is acknowledged or ac ted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the posi tive temperature coefficien t of vt with the negative temperature coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or info rmation processing system measured in hertz. 2. the width of the spectral region over which an amplifie r (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field ) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and ca rrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed freq uency and duty cycle. a clo ck is sometimes used to synchronize different logic blocks. comparator an electronic circuit that pr oduces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language.
cy8c201a0 document number: 001-54607 rev. *g page 33 of 38 configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is cont rolled by a piezoelectric crystal. typically a piezoelectric crys tal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communi cations, typically performed using a linear feedback shift register. similar calculations may be used for a va riety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows you to analyze the operation of the system under development. a debugger usually allows the developer to step through t he firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counte r, timer, serial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital (adc) converter performs the reverse operation. duty cycle the relationship of a cl ock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulat ion of) the functions of o ne system with a different syst em, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc devic e. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volat ile technology that provides you the programmability and data storage of eproms, plus in-system erasability. non-vola tile means that the data is retained when power is off. flash block the smallest amount of flas h rom space that may be pr ogrammed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events per unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, re spectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductor s (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the origi nal system was created in the early 1980s as a battery control inte rface, but it was later used as a si mple internal bus system for building control electronics. i2c uses only two bi-directional pi ns, clock and data, both running at +5 v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator t hat allows you to test the project in a hard ware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a de vice that introduces data into or extracts data from a system. glossary (continued)
cy8c201a0 document number: 001-54607 rev. *g page 34 of 38 interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a wa y that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority an d individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the ti ming of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more si gnal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interr upt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated ci rcuit chip that is designed prim arily for control systems and produc ts. in addition to a cpu, a microcontroller typically includes memory, timing circuits, a nd i/o circuitry. the reason for this is to permit the realization of a controller with a mini mal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristic s of any entity such as voltage, current, or data. oscillator a circuit that may be crystal contro lled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a bi nary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between t he logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer gen erated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the vo ltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programm able system-on-chip? is a trademark of cypress. glossary (continued)
cy8c201a0 document number: 001-54607 rev. *g page 35 of 38 psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a func tion of the appl ied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specif ic capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware re set and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. shift register a memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external in terface. the controlling dev ice is called the master device. sram an acronym for static random access memory. a memo ry device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly altered or unt il power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or ac ted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output can ad opt three states: 0, 1, and z (high-imp edance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter tr anslates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardware/fi rmware peripheral functions that take ca re of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the regist er map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. registers in bank 1 ar e most likely to be modified only during the initialization p hase of the program. glossary (continued)
cy8c201a0 document number: 001-54607 rev. *g page 36 of 38 v dd a name for a power net meaning "voltage drain." the mo st positive power supply sig nal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued)
cy8c201a0 document number: 001-54607 rev. *g page 37 of 38 document history page document title: cy8c201a0, capsense ? express? slider capacitive controllers document number: 001-54607 rev. ecn orig. of change submission date description of change ** 2741726 slan / fsu 07/21/2009 new data sheet. *a 2821828 sshh / fsu 12/4/2009 added contents . updated layout guidelines and best practices (updated dimensions for slider design (added note 15 and referred in t he parameter column)). updated absolute maximum ratings (added f32k u, t powerup parameters and their details). updated electrical specifications (updated dc electrical specifications (updated dc flash write specifications (updated note 17 ))). *b 2892629 njf 03/15/2010 updated absolute maximum ratings (added t baketemp and t baketime parameters and their details). updated pin definitions (added a note ?for information on the preferred dimensions for mounting qfn packages, see the "application notes for surface mount assembly of amkor's microleadframe (mlf) packages" available at http://www.amkor.com .? below the column). *c 3043236 arvm 09/30/10 updated pin definitions (added note 2 and referred the same note in all gp1[1] and gp1[2] pins). updated pin definitions (added note 3 and referred the same note in all gp1[1] and gp1[2] pins). updated typical circuits (updated figure 3 (replaced with updated one)). updated absolute maximum ratings (removed f32ku, t powerup parameters and their details). updated electrical specifications (updated ac electrical specifications (added ac chip-level specifications section)). *d 3085081 njf 11/12/10 updated electrical specifications (updated dc electrical specifications (updated dc gpio specifications (removed sub-section ?2.7-v dc spec for i2c line with 1.8 v external pull-up?), added dc i2c specifications ), updated ac electrical specifications (updated ac i 2 c specifications (updated figure 10 (no specific changed were made to i 2 c timing diagram. updated for clearer understanding.)))). updated solder reflow specifications . added acronyms and units of measure . added reference documents and glossary . updated in new template. *e 3276234 arvm 01/20/11 updated layout guidelines and best practices (updated ta b l e 2 (removed ?overlay thickness-buttons? category), added the following statement after table 2 ? ?the recommended maximum overlay thickness is 5 mm (with external cs int )/ 2 mm (without external cs int ). for more details refe r to the section ?the integrating capacitor (cint)? in an53490 ?.). updated capsense constraints (removed the parameter ?overlay thickness?). updated solder reflow specifications (updated table 15 ). *f 3390450 slan 09/30/2011 post to external web. *g 3631370 vair / slan 05/31/2012 updated pin definitions (updated description of xres pin). updated pin definitions (updated description of xres pin). updated typical circuits (updated figure 4 (added note 5 and referred the same note in figure 4 )). updated in new template.
document number: 001-54607 rev. *g revised may 31, 2012 page 38 of 38 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c201a0 ? cypress semiconductor corporation, 2009-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY8C201A0-LDX2I

	To Download CY8C201A0-LDX2I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .